1. Field of the Invention
This invention relates generally to computer systems, and more particularly to computer systems having multiple processors, each processor having its own independent operating system.
2. Description of the Prior Art
Traditional von Neumann computers, working in parallel, represent the bulk of multiprocessing architectures to date. In the von Neumann architecture, established about a generation ago, controlled logic routes instructions and data from a common memory to a central processing unit that manipulates the data and sends the results back to memory. In this type of an architecture the limiting factor in processing speed and in diversity of programs that can be handled simultaneously is the central processing unit (CPU). To minimize this difficulty different types of computers have been built employing multiprocessor or multiprogramming architectures that are based on the fundamental von Neumann architecture. The bulk of these multiprocessor architectures utilize multiple CPUs, working in parallel, to apply multiple instruction streams to multiple data streams. These machines run the gamut from simple master-slave coprocessor systems to extensive networks.
In one such architecture the CPUs are coupled to a bus and all traffic must travel on that bus. Consequently the bus becomes the system's limiting component as the number of processors grows. To alleviate such bus congestion a shared memory type of architecture is utilized. In this architecture the shared random access memory (RAM) usually has two ports, one of which connects to a local bus and the other to a system bus. This dual-bus hierachy architecture works best when the two kinds of data streams are reasonably balanced and the load distribution among processors does not require complex arbitration schemes. This balance is rarely achieved in practice and resort must be had to priority type architectures. Under this type architecture each processor requesting the bus must place their encoded priority on the bus which is then examined to find the highest priority request which is entitled to the bus. Once again as the number of processors gorws the system becomes slower and more complex.
At the other end of the spectrum from this autocratic type of multiprocessor environment is the egalitarian type. In an egalitarian system all processors are created equal. In an egalitarian system each machine has its own operating system which governs communications between computers through input/output channels. In between these two extremes, the autocratic and the egalitarian architecture there are many shades, such as the well-known master/slave relationship which simplifies the resolution of conflicts, such as bus contention or priority assignment. One such type architecture, utilizing a combination of egalitarian and autocratic type architecture has multiple processors with each processor having its own operating system. These processors share a common memory and communicate with each other via a semophore mechanism. Additional multiprocessing architectures are described in a special report entitled "Multiprocessing Sytems", published in Electronic Design Magazine on Mar. 22, 1984.
The Honeywell microSystem 6/10 computer system adopted an architecture which was a novel combination of architectures described above and in the Electronic Design article. Basically it comprised an LSI-6 processor with its own MOD400 operaing system; an Intel type 8086 processor also having an independent operating system, such as the MSDOS or the CPM-86; and a Motorola 6809 processor. All these processors shared a common memory. Additionally the Motorola 6809 processor acted as an input/output (I/O) processor and had its own local memory. In order to eliminate much of the complexity of the type of architectures described supra, the microSystem 6/10 system was designed so that the Honeywall LSI-6 processor, which is a firmware based processor, would utilize 20-24% of the memory band width*; whereas the Intel 8086 processor, which was a slower software based machine, would utilize 70-74% of the memory band width. The Motorola processor (the I/O processor) having its own memory would utilize less than 1% of the memory band width of the shared processor. Accordingly in this architecture if there were no personal computer option (i.e. the Intel 8086 processor), the Honeywell LSI-6 processor would be under-utilized. This architecture was deliberately chosen so that the microSystem 6/10 system could have a personal computing option by adding the Intel 8086 CPU which could run commodity software with its MSDOS or CPM-86 operating system. Additionally the LSI-6 CPU, with its MOD400 or MOD200 operating system, or other operating systems, would simultaneously run software written for the Honeywell Level 6 Series. With this type of architecture the personal computer (Intel 8086) could utilize any memory cycles which the LSI-6 computer or the Motorola 6809 did not utilize. This would amount to approximately 75% of all memory cycles. This is a very synergistic type of mix of processes. This is accomplished by giving absolute memory utilization to the LSI-6. It is designed to use about 20-24% of the memory band width. If the LSI-6 wishes to use a memory cycle, he gets that cycle. If not, then that cycle is free for anyone else. The next-in-line would be the Motorola 6809 processor. However since its utilization is less than 1% of memory band width, the 8086 personal computer should utilize the bulk of the memory cycles. Because the 8086 processor cannot fully access the memory space reserved for the LSI-6, and because I/O operations are performed by the Motorola 6809 processor which can be requested directly only by the LSI-6 processor, communication is required between the 8086 and LSI-6 by messages transmitted through common memory. In order to synchronize this utilization of memory, a semaphore architecture is utilized. When the 8086 personal computer wants service (I/O transfer, etc.), it places a message in the semaphore; i.e., mailbox. In order to respond to requests for service from the 8086 personal computer, the LSI-6 computer has to monitor the semaphore/malibox to determine if a request is present and the type of request. The LSI-6 computer with standard programming techniques requires 500 .mu.s and 150 memory accesses to check and test this semaphore/mailbox once. However the LSI-6 computer runs on a 649 ns cycle; thus checking for an event every 500 .mu.s is not very efficient. Moreover utilization of 150 or more memory accesses by the LSI-6 computer cuts down on the memory band width available to the 8086 personal computer. In some instances the LSI-6 computer utilized over 90% of the memory band width although it was designed to utilize 20-24% of memory band width. Accordingly the personal computer could not run its programs with its operating system at full speed since it required at least 70-74% of the memory band width. What was needed, therefore, was a means of speeding up the monitoring of the semaphore so that the microSystem 6/10 system could operate under its uniquely designed architecture. FNT * Memory band width is the number of clock cycles available to perform a memory operation in a given amount of time.